Plasma display panels are presently in commercial use as digitally addressable information display devices. The panel itself typically consists of two glass plates with a gas mixture sealed between them. A plurality of X-axis electrodes extend in a mutually parallel array on an interior substrate of one plate, and a plurality of Y-axis electrodes extend in a mutually parallel array on the interior of the other plate. The X-axis electrodes are at a 90.degree. angle to the Y-axis electrodes, thereby forming a plurality of intersections between the X-axis and Y-axis electrodes. A typical commercially available AC plasma panel has 512 X-axis electrodes and 512 Y-axis electrodes, yielding 262,144 intersections or cells.
When a voltage of between 180 and 200 volts is applied across an X-axis electrode and a Y-axis electrode, a discharge in the gas occurs at the cell formed by the electrodes, causing a pulse of light to be emitted at this point. Simultaneously, a charge is collected on the cell walls, which results in the cell being an "on" cell. Once such a discharge has been produced and the cell is turned "on", the collected wall charge acts to continue the discharging when a lesser AC sustain voltage is applied between the electrodes. In an "on" cell, the gas will discharge and the cell will emit a pulse of light at each transition of the applied AC sustain waveform. The sustain voltage, however, is insufficient to initiate a discharge at an X-Y intersection. This phenomenon is known as inherent memory, and was originally disclosed by Baker et al in U.S. Pat. No. 3,499,167, and by Bitzer et al in U.S. Pat. No. 3,959,190. By precisely timing, shaping, and phasing multiple alternating voltage waveforms supplied to X and Y axes electrodes, the generation, sustaining, and erasure of light emitting gas discharges at selected locations on the plasma display panel can be controlled.
The state of the art of drive systems for plasma panels is represented by patent application Ser. No. 412,205, filed Aug. 27, 1982, which is a continuation of patent application Ser. No. 166,579, filed July 7, 1980 (now abandoned), by Joseph T. Suste, describing a Drive System For A Plasma Panel utilizing only three voltage levels, and patent application Ser. No. 258,757, filed Apr. 29, 1981, by Larry M. Weber, describing a MOSFET Sustainer For A Plasma Panel Drive System. These two patents are assigned to the assignee of the present invention, and both of these specifications are hereby incorporated herein by reference.
These systems utilize Texas Instruments integrated circuit driver chips to drive the electrodes of the plasma panel. These chips, each capable of driving 32 electrodes on the panel, are types SN75500 and SN75501. These are the only currently available driver chips, and they have several serious design problems that the manufacturer cannot remedy at this time. The only alternative to using these driver chips is to use a resistor-diode matrix, wherein each electrode is connected to two diodes and a resistor. For 512 lines there are also 16 high voltage pulser circuits and 32 high voltage switch circuits required. In order to drive a 512.times.512 plasma display panel, the discrete electronics alternative to the Texas Instruments driver chips takes up 650 square inches of printed circuit board. Using the Texas Instruments driver chips, the number of components required is reduced by a factor of 100, and the printed circuit board area required is reduced by a factor of 5. Since assembly and test costs are greatly reduced by using the Texas Instruments drive chips, it is no longer economically feasible to build plasma panel display systems without using the driver chips.
The most significant problem encountered in using the Texas Instruments driver chips is that of dissipating the power consumed in these chips. Power dissipation can be divided into 5 areas: low voltage logic power, quiescent power, level shifting boost power, parasitic power, and notch dissipation power.
Low voltage logic power is the power used to control the logical switching process of the driver chips. This power is not an appreciable cause of excess power dissipation within the driver chips.
Quiescent power is the power consumed by the high voltage switching components within the chip while the chip is turned on but not performing any type of operation. Since the driver chips are being used to switch 100 volts, even a small amount of quiescent current drawn by the chips will result in a fairly large amount of power being dissipated in the chips. The quiescent current for the SN75500 chip is 2 mA, and the quiescent current for an SN75501 driver chip is 3 mA. The quiescent power consumed by the chips is 200 mW and 300 mW, respectively. Since a 512.times.512 plasma display panel system requires 16 of each of the two types of chips, the quiescent power of the system's driver circuitry will be 8 watts. This power level typically represents 10 to 20% of the entire plasma display panel system power.
Level shifting boost power is the power consumed by the chip when it is being switched between output stages. The chips use a boost current of 2 mA to switch from the low state to the high state. If all of the 32 outputs of the driver chip are to be switched, a 2 mA current will be drawn by a switching transistor in the circuitry of each output at a duty cycle of 2.5%, which results in a time-averaged level of 192 mW of power per chip being consumed when switching at a standard rate of 50 kHz.
The next major power dissipation problem is created by the existence of parasitic transistors in the driver chips. A parasitic transistor is an inadvertently created np or pn junction which is inherent in the forming of a pn or np diode. In order to better understand the problem it is necessary to understand the basic operation of the driver chip switching circuit.
The design of the Texas Instruments driver chips utilizes 32 totem-pole output stages in order to perform the switching operation. A totem-pole is basically two switching transistors connected in series, with their common lead being the output of the circuit. The second switch lead of one transistor is connected to high voltage, and the second switch lead of the second transistor is connected to ground, or low voltage. By ensuring that only one of these transistors is turned on at a time, the output of the circuit can be switched from high voltage to low voltage.
The transistors used in the totem-pole output stages of the Texas Instruments driver chips are N-channel enhancement DMOS (double diffused metal oxide silicon) transistors, which are the key for fabricating high voltage drivers and low voltage control logic on the same chip. The Texas Instruments design utilizes a pair of clamp diodes on the output of the totem-pole to prevent the output level from rising above the high voltage or below the low voltage. When these clamp diodes are fabricated, parasitic bi-polar transistors are formed along with the diodes. These parasitic transistors, inherent in junction isolation IC technology, result from the existence of an additional np or pn junction being formed with the clamp diodes. The clamp diodes are the base-emitter junction of the parasitic transistor, and the additional junction is the base-collector junction. The resulting transistor has its emitter connected to the common output, its base connected to either the high or low voltage, and its collector connected to the other voltage level. This has the effect of placing a 100-volt drop across the base-collector junction of each of these parasitic transistors. Therefore, when the base-emitter junction is forward biased, current will flow between the base and the collector, causing power to dissipate in this junction. While Texas Instruments endeavored to make the parasitic transistor's beta (ratio of collector current to base current) as low as possible, the typical beta of 0.4 which resulted was not low enough to eliminate the parasitic transistor as a power dissipation problem.
When the system performs a switching operation, there is a current spike drawn by the panel of 20 mA. Therefore, a current of 8 mA (0.4.times.20 mA) will flow through the base-collector junction, resulting in an instantaneous power dissipation of 800 mW for each of the 32 outputs of the chip. The only thing which prevents the chip from immediately self-destructing is the fact that the current spike lasts only 300 nS. For purposes of comparison, the clamping diode portion of the parasitic transistor dissipates only 50 mW of instantaneous power, less than one-tenth that dissipated by the parasitic transistor. The time-averaged parasitic power consumed may be as high as 384 mW per chip.
Another type of power dissipated by the driver chips is notch dissipation power. The term "notch" derives from the level of voltage supplied by the driver chip's totem-pole outputs.
If an oscilliscope is placed across the voltage supplied to the electrode and ground, the trace generated when a voltage pulse is sent to the electrode would initially rise to close to 100 volts, and then, for a fraction of a second, will drop several volts before returning to the 100-volt level. The drop in voltage level, being very short, makes the oscilliscope trace look like it had a notch removed from it; hence, the term voltage notch.
The voltage notch is caused by the high current drawn by the electrodes, which is approximately 20 mA if all 512 cells are being supplied with the voltage pulse. This current causes the transistors in a driver chip totem-pole output to develop a voltage drop which causes less than the 100 volts to be applied to the electrode. The high transistor in the totem-pole of the Texas Instruments chips will develop an 8.5-volt drop, and the low transistor will develop a 2.5-volt drop.
Notch dissipation power is the power dissipated in the switching transistors of the totem-pole, and the large amount of notch dissipation power is caused by the excess voltage drop across the switching transistors. Since the voltage drops are relatively high, a considerable amount of power must be dissipated by the switching transistors. The average power per fully loaded electrode is 1.3 mW, and the power dissipated in these switching transistors due to notch dissipation power may reach a time average level of about 39 mW per driver chip.
The cumulative effect of all of the above power dissipation problems in the integrated circuit chip is that the power dissipated will cause the chip to operate at a fairly high temperature. It has been observed that the temperature rise of the driver chip case is over 75.degree. C. in an ambient environment of 23.degree. C. Since it is generally required that the drive electronics be encased in a sealed unit, the possibility of failure due to power dissipation in the driver chips becomes even greater. It has been found that the operating life of a driver chip in a circuit using the above-described advanced technology is only hours to days.
The next problem present in the Texas Instruments driver chips is an output pulse fall time which is so fast that it generates high instantaneous currents which will cause noise generation, disrupting system performance. Both chips have fall times of 30 to 50 nS. The instantaneous current may be calculated by using the formula i=c.multidot.dv/dt. The capacitance for a typical 512.times.512 panel is 3500 pf, the voltage change is 100 V in 50 nS. The instantaneous current is thereby 7 A, a tremendous amount even for a short time. This current will cause a voltage to be induced in nearby interconnecting wires, and this voltage will cause logic errors in the system.
In selecting the rise time and fall time of the voltage pulse which is supplied to the electrodes, there is a compromise involved. If the transition between voltage levels is too slow, the plasma panel display cells, or intersections between X and Y electrodes, will exhibit poor memory and light emitting characteristics. Under normal circumstances, the discharge causing the emission of light pulse and the execution of a write or erase operation occurs at a point on the pulse where the peak voltage level of the pulse has been reached. However, if the transition time is too slow, this discharge will have a tendency to occur during the rising portion of the pulse, before the peak voltage has been reached. The result is a weak discharge causing poor memory and poor light emitting characteristics in the plasma panel system.
In contrast, too fast a transition time will cause noise to be generated in the system, given the relatively high voltage of about 100 volts that is being switched. The Texas Instruments driver chips have fall times of 30 to 50 nS. If an electrode of the plasma panel is charged to 100 volts in 50 nS, the instantaneous current flowing through the charging circuit is approximately 7 amps. Since the physical size of a typical plasma display panel is 1 foot.times.1 foot, the presence of 512 X-electrodes and 512 Y-electrodes in that area indicates that these electrodes are extremely close together. Interconnecting wires to the plasma panel have been found to have approximately 1 nH of inductance and the extremely high instantaneous current will therefore cause voltage drops of several volts in adjoining wires, which will result in logic errors in the plasma display panel system.
Transition times of between 200 and 400 nS are generally considered ideal. While the rise times of the Texas Instruments driver chips fall within this range, the fall times are much too fast. The result of using the Texas Instruments driver chips is an unacceptably large number of logic errors.
The next problem associated with these driver chips is caused by the voltage notch described above. In addition to being a power dissipation problem, the large voltage notch imposes constraints on the design of the system. The voltage notch, particularly the 8.5 V drop in the high state, cause the voltage applied to the panel to be dropped from the desired 100 V to about 92.5 V, when the selected electrode is being driven to the high state.
This lesser voltage level is very near the absolute minimum required voltage, and any further losses will cause a failure in the operation of the panel. Since no further loss can be tolerated, precise regulation of the power supply, the use of high-precision components, and careful layout of the system are mandatory. The plasma display panel itself may have to meet more rigorous standards. All this leads to higher product cost, and less flexibility in making system trade-offs.
In addition, a 1024.times.1024 panel could not be driven by these driver chips, since such a panel would draw approximately 40 mA from each IC, increasing the voltage notch. Therefore, these chips are limited to driving a panel no larger than a 512.times.512 size.
There is also a logic error in the SN75501 driver chip. The chip is switched from its low output to its high output by a current booster (responsible for the boost current power dissipation problem described above). This current booster is essentially a bi-level current source. When the driver chip output is in its low state, 10 microamps are supplied. When a logic signal indicates the driver chip is to go high, the current booster supplies a 2 mA boost current, causing the pull-up output transistor to be driven on.
The logic error occurs when the strobe input pin of the chip (used for the address pulse input) is held low and the sustain pin (used for the distributed conditioning input) is brought high. This logic state should cause the driver output to quickly go to its high state. The boost current, however, is not applied, and the output is a slowly rising ramp, taking 5 to 10 microseconds to reach the high state.
Since an operation on the panel may take less than the 5 to 10 microsecond rise time of the pulse, it is not of any use in addressing the panel. In the past, systems have been designed around this flaw resulting in inefficient and inconvenient operations being necessitated.